In complex computer systems having a plurality of microprocessors or central processing units (CPU's), it is common practice to implement a two-tiered addressing scheme comprising virtual addresses and physical addresses. Virtual addresses correspond to addresses generated by a CPU in the course of executing a program, and physical addresses correspond to addresses at which actual memory locations can be found. In order for the CPU (which uses virtual addresses) to get access to an actual memory location, some mechanism is required for mapping or translating the virtual addresses to the physical addresses. This translation is usually achieved by using Translation Data Structures (TDS) which contain the entire set of virtual-to-physical address translations. The TDS typically resides within the main memory associated with the particular CPU.
It is possible to consult the TDS each time a translation is needed but such a translation scheme is relatively slow. To improve system performance, an intermediate memory, known as a Translation Lookaside Buffer (TLB), is typically disposed between the CPU and main memory to store the most recently accessed address translations. The TLB in essence acts as an address translation cache memory. The TLB typically resides within a memory management unit (MMU) which, in addition to translating addresses, performs a variety of memory management functions for a corresponding CPU.
A TLB is typically implemented using Content Addressable Memories (CAM's) and Static RAM's (SRAM's) because of the high speed capabilities of these components. While CAM's and SRAM's are faster than most other memory components, they are made of structurally "weaker" devices, which makes them more vulnerable to transient errors than other devices such as standard logic gates. Consequently, the data stored within a TLB stand a higher chance of being corrupted by hardware defects than data in other components. Because of the higher probability of data corruption, a system utilizing a TLB needs to have some means for detecting and handling the hardware errors that may arise. Otherwise, the failure of a single cell in the TLB may cause the system to fail or, at the very least, may require that the entire MMU be replaced. Replacing the entire MMU for such a minor defect would be a waste of valuable resources. To optimize the reliability of the system and to minimize waste, a means for detecting and handling errors in the translation table of a MMU is needed.